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Kostas Siozios, PhD
ksiop@microlab.ntua.gr

Post-Doctoral Researcher
Microprocessors and Digital Systems Lab
School of Electrical and Computer Engineering
Department of Computer Science
National Technical University of Athens (NTUA)
Greece

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Research


"It is not the strongest (ASIC) of the species that survive, nor the most intelligent (CPU), but the one most responsive to change (RECONFIGURABLE)"
Charles Darwin


Research Topics
* Reconfigurable architectures
* 3D architectures
* Low-power design
* CAD algorithms and tools
* Network-on-Chip (NoC)

 
Publications
 
PhD Thesis
K. Siozios, "Software/Hardware Co-Design for Low-Power Reconfigurable Architectures", PhD Thesis, Department of Electrical and Computer Engineering, Democritus University of Thrace, 2009, Greece (only in Greek).
 
3D Integration
2009 K. Siozios, V. Pavlidis, and D. Soudris, “A Software-Supported Methodology for Exploring Interconnection Architectures Targeting 3-D FPGAs”, Proceedings in Design, Automation and Testing in Europe (DATE), pp. 172-177, April 2009, Nice, France
2009 K. Siozios, A. Papanikolaou, A. Bartzas and D. Soudris, “System-Level Exploration of 3-D Interconnection Schemes”, Design, Automation and Testing in Europe (DATE) Friday Workshop on 3D Integration, Friday 24th April 2009, Nice, France.
2009 K. Siozios and D. Soudris, "A Novel Methodology for Exploring Interconnection Architectures Targeting 3-D FPGAs", in 3rd HiPEAC Workshop on Reconfigurable Computing (WRC), 2009, Phafos, Cyprus
2009 K. Siozios, D. Soudris and G. Economakos, "Three-Dimensional FPGA Architectures: A Shift Paradigm for Energy-Performance Efficient DSP Implementations", 16th International Conference on Digital Signal Processing (DSP), 5-7 July 2009, Santorini, Greece
2008 K. Siozios, A. Bartzas and D. Soudris , "Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology", International Journal of Reconfigurable Computing, Vol. 2008, Article ID 76942, 18 pages, DOI: 10.1155/2008/76942
2008 K. Siozios, A. Papanikolaou and D. Soudris, "A method and tool for early design/technology search-space exploration for 3D ICs", in IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2008, Rhodes, Greece
2007 K. Siozios, K. Sotiriadis, V. F. Pavlidis and D. Soudris, "A Software-Supported Methodology for Designing High-Performance 3D FPGA Architectures", IPIP International Conference on Very Large Scale Integration (VLSI-SoC), pp. 54-59, 2007, USA
2007 K. Siozios, K. Sotiriadis, V. F. Pavlidis and D. Soudris, "Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support", 17th International Conference on Field Programmable Logic and Applications (FPL), pp. 652-656, 2007
 
Heterogeneous FPGAs
2009 K. Siozios and D. Soudris, "Designing a Novel High-Performance FPGA Architecture for Data Intensive Applications", Journal of Real-Time Image Processing, Springer Berlin/Heidelberg, DOI 10.1007/s11554-008-0099-4, pp. 155-166, 2009
2008 K. Siozios, D. Soudris and A. Thanailakis, "Designing a General-Purpose Heterogeneous Interconnection Architecture for FPGAs", Journal of Low Power Electronics (JOLPE), Vol. 4, No. 1, pp. 34-47, April 2008
2008 K. Siozios, D. Soudris and A. Thanailakis, "A Software-Supported Methodology for Designing General-Purpose Interconnection Networks for Reconfigurable Architectures", International Journal of Electronics, Circuits and Systems (IJECS), Vol. 4, No. 3, pp. 187-199, Summer 2008
2007 K. Siozios, S. Mamagkakis, D. Soudris and A. Thanailakis, "Designing Heterogeneous FPGAs with Multiple SBs", International Workshop on Applied Reconfigurable Computing (ARC), pp. 91-96, 2007, Brazil
2006 K. Siozios and D. Soudris, "Wire Segment Length and Switch Box Co-Optimization for FPGA Architectures", 16th International Conference on Field Programmable Logic and Applications (FPL), pp. 1-4, 2006, Spain
2006 K. Siozios, D. Soudris and A. Thanailakis, "Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources", 16th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 403-414, 2006, France
2006 K. Siozios, K. Tatas, D. Soudris and A. Thanailakis, "Platform-based FPGA Architecture: Designing High-Performance and Low-Power Routing Structure for Realizing DSP Applications", 13th Reconfigurable Architectures Workshop (RAW), pp. 10, 2006, Greece
2006 K. Siozios, D. Soudris and A. Thanailakis, "A Novel Methodology for Designing High-Performance and Low-Power FPGA Interconnection Targeting DSP Applications", ΙΕΕΕ International Symposium on Circuits and Systems (ISCAS), pp. 4383-4386, Greece, 2006
 
FPGA Design and Supporting CAD Tools
2008 K. Siozios, "Σχεδιασμός Υλικού και Λογισμικού Επαναδιαμορφούμενων Συστημάτων VLSI με Χαμηλή Κατανάλωση Ισχύος", Τμήμα Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών, Δημοκρίτειο Πανεπιστήμιο Θράκης, Ξάνθη, 2008
2007 K. Tatas, K. Siozios, and D. Soudris, "Survey of Fine-Grain Reconfigurable Architectures and Processors", Chapter 1 in "Fine- and Coarse-Grain Reconfigurable Systems", Editors: S. Vassiliadis and D. Soudris, Springer, 2007, pp. 3-88
2005 K. Siozios, G. Koutroumpezis, K. Tatas, N. Vassiliadis, V. Kalenteridis, H. Pournara, I. Pappas, D. Soudris, S. Nikolaidis, S. Siskos, and A. Thanailakis, "The AMDREL Project in Retrospective", IFIP International Conference on Very Large Scale Integration (VLSI-SoC), 2005, Australia
2005 K. Siozios, K. Tatas, G. Koutroumpezis, D. Soudris, and A. Thanailakis, "An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform", 15th International Conference on Field Programmable Logic and Applications (FPL), pp. 658-661, 2005, Finland
2005 D. Soudris, S. Nikolaidis, S. Siskos, K. Tatas, K. Siozios, G. Koutroumpezis, N. Vasiliadis, V. Kalenteridis, H. Pournara, I. Pappas, and A. Thanailakis, "AMDREL: A Novel Low-Energy FPGA Architecture and Supporting CAD Tool Design Flow", Proceedings of ASP-DAC 2005, Asia South Pacific Design Automation Conference (Design Contest), pp. D3-D4, 2005, China
2004 V. Kalenteridis, H. Pournara, K. Siozios, K. Tatas, I. Pappas, S. Nikolaidis, S.Siskos, D. J. Soudris and A. Thanailakis, "A Complete Platform and Toolset for System Implementation on Fine-Grain Reconfigurable Hardware", Microprocessors and Microsystems, Special Issue on Field-Programmable Gate Arrays (FPGAs): Applications, Algorithms and Tools, Elsevier Publishers, Vol. 29/6, pp. 247-259, 2004
2004 V. Kalenteridis, H. Pournara, K. Siozios, K. Tatas, I. Pappas, S. Nikolaidis, S. Siskos, D. J. Soudris and A. Thanailakis, "An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development", Proceedings of 11th Reconfigurable Architectures (RAW), pp. 138, April 26-27, 2004, Santa Fe, New Mexico, USA
2004 I. Pappas, N. Vassiliadis, V. Kalenteridis, H. Pournara, S. Nikolaidis, S. Siskos, K. Siozios, G. Koutroumpezis, K. Tatas, D. J. Soudris and A. Thanailakis, "Fine-Grain Reconfigurable Platform: FPGA Hardware Design and Software Toolset Development", Proceedings of 2nd Conference on Microelectronics Microsystems and Nanotechnology, pp. 352-356, 2004, Greece
2003 K. Siozios, "Σχεδιασμός Βασικής Δομικής Μονάδας και Ανάπτυξη Εργαλείων Σχεδιασμού για Ενσωματωμένο FPGA", Τμήμα Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών, Δημοκρίτειο Πανεπιστήμιο Θράκης, Ξάνθη, 2003
 
CAD Algorithms
2009 K. Siozios and D. Soudris, "A Novel Algorithm for Temperature-Aware P&R on 3-D FPGAs", Post Conference Book of IEEE/VLSI-SoC 2008, Editos, D. Soudris, C. Piguet and R. Reis, Springer Publishers
2009 K. Siozios, D. Soudris and A. Thanailakis, "A Novel Allocation Methodology for Partial and Dynamic Bitstream Generation of FPGA Architectures", accepted for publication in Journal of Circuits, Systems, and Computers (accepted for publication)
2008 K. Siozios and D. Soudris , "A Power-Aware Placement and Routing Algorithm Targeting 3D FPGAs", Journal of Low-Power Electronics (JOLPE), Vol. 4, No. 3, pp. 275-289, December 2008
2008 K. Siozios and D. Soudris, "A Novel Algorithm for Temperature-Aware P&R on 3D FPGAs", in IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2008, Rhodes, Greece
2008 K. Siozios and D. Soudris, "A Power-Aware Placement and Routing Algorithm Targeting to 3D FPGAs", International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), September 10-12, 2008, Lisbon, Portugal - Invited paper
2007 K. Siozios and D. Soudris, "A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs", IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 55-60, 2007, Brazil
2007 D. Soudris, K. Tatas, K. Siozios, G. Koutroumpezis, S. Nikolaidis, S. Siskos, N. Vasiliadis, V. Kalenteridis, H. Pournara and I. Pappas, "AMDREL: A Novel Low-Energy FPGA Architecture and Supporting CAD Tool Design Flow", Chapter 3 in "Fine – and Coarse-Grain Reconfigurable Systems", Editors: S. Vassiliadis and D. Soudris, Springer, 2007, pp. 152-180
2007 K. Siozios and D. Soudris, "A Temperature-Aware Mapping Methodology for FPGAs", ACM International Symposium on Field-Programmable Gate Arrays (FPGA), 2007, USA
2006 K. Siozios, K. Tatas, D. Soudris and A. Thanailakis, "A Novel Methodology for Designing High-Performance and Low-Energy FPGA Interconnection Architecture", 14th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), pp. 224, 2006, USA
2006 K. Siozios, D. Soudris and A. Thanailakis, "Efficient Power Management Strategy for FPGAs Using a Novel Placement Technique", IFIP International Conference on Very Large Scale Integration (VLSI-SoC), pp. 204-209, 2006, France
2005 K. Siozios, G. Koutroumpezis, K. Tatas, N. Vasiliadis, V. Kalenteridis, H. Pournara, I. Pappas, D. Soudris, A. Thanailakis, S. Nikolaidis and S. Siskos, "A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications", IEICE Transactions on Information and Systems, Special Issue on Recent Advances in Circuits and Systems, Vol. E88-D, No. 7, July 2005, pp. 1369-1380
2005 K. Siozios, G. Koutroumpezis, K. Tatas, D. Soudris, and A. Thanailakis, "DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and its Software Tool Implementation", 12th Reconfigurable Architectures Workshop (RAW), pp. 165b, 2005, USA
2004 K. Siozios, G. Koutroumpezis, K. Tatas, D. Soudris, and A. Thanailakis, "A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development", Proceedings of 14th International Conference on Field Programmable Logic and Applications (FPL), pp. 1116-1118, 2004, Belgium
 
Network-on-Chip
2009 A. Bartzas, K. Siozios and D. Soudris, "Topology Exploration and Buffer Sizing for Three-Dimensional Networks-on-Chip", Design, Automation and Testing in Europe (DATE) Friday Workshop on 3D Integration, Friday 24th April 2009, Nice, France.
2008 A. Bartzas, K. Siozios, and D. Soudris, "Three Dimensional Network-on-Chip Architectures", Chapter 2, in "Networks-on-Chips: Theory and practice", CRC Press, 2008
2007 A. Bartzas, N. Skalis, K. Siozios, D. Soudris, "Exploration of Alternative Topologies for Application-Specific 3D Networks-on-Chip", Workshop on Application Specific Processors (WASP), October 4, 2007
 
Power Optimization
2003 K. Tatas, K. Siozios, D. Soudris, and A. Thanailakis, "Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms", Proceedings of 13th International Conference on Field Programmable Logic and Applications (FPL 2003), pp. 1032-1035, Sep. 1-3, 2003, Lisbon, Portugal
2003 K. Tatas, K. Siozios, N. Vasiliadis, D. J. Soudris, S. Nikolaidis, S. Siskos, and A. Thanailakis, "FPGA Architecture Design and Toolset for Logic Implementation", Proceedings of 13th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2003), pp. 607-616, Sep. 10-12, 2003,Torino, Italy
2003 K. Tatas, K. Siozios, D. Soudris, K. Masselos, K. Potamianos, S. Blionas and A. Thanailakis, "Power Optimization Methodology for Multimedia Applications Implementation on Reconfigurable Platforms", Proceedings of 13th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2003), pp. 430-439, Sep. 10-12, 2003, Torino, Italy
 
Programming
2001 A. Karakos and K. Siozios, "Secure Networking Using Mobile IP", Proceedings of 8th Panhellenic Conference on Informatics, pp. 284-293, 8-10 November 2001, Nicosia, Cyprus
2003 K. Siozios, P. Efraimidis and A. Karakos, "Design and Implementation of a Secure Mobile IP Architecture", Proceedings of 9th Panhellenic Conference in Informatics, pp. 269-279, Thessaloniki, Greece, 21-23 November 2003
 

Last Update: 15 July 2009
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