Throughout the TEAChER project we aim to develop educational material for teaching topics related to the 2D and 3D reconfigurable architectures. More specifically, during these lessons we plan to address both architectural-oriented issues, topics related to CAD algorithms, as well as efficient ways for digital design with the usage of advanced programming languages. As there are different demands for training in this domain, the developed material will be appropriately tuned for the target audience, spanning from undergraduate studies up to PhD. For this purpose, we plan to prepare slides, presentation, books, CD/DVDs, as well as laboratory exercises for each of these topics. Apart from the conventional educational methods that will be taken into consideration during the preparation of this material, we aim to develop a virtual classroom, where students will have remote access both to theoretical, as well as laboratory infrastructure. Another outcome of this project is expected to be a number of workshops and summers schools, where Professors and key persons from related industry will give lectures.

Starting from an application, initially we perform architecture-level exploration in order to determine the most suitable reconfigurable architecture for application implementation. During this analysis, a number of application's properties are identified. Among others, the memory requirements, the demands for supporting high-speed connectivity among distinct kernels, as well as the existence, or not, of complex arithmetic operations (e.g. floating-point operations) are identified. The conclusions of this step provide an overview for the architectural organization of the target reconfigurable device. These parameters are appropriately handled in order to instantiate in VHDL (VHSIC Hardware Description Language) the architecture description of the FPGA. An initial form of this description regarding the 2-D FPGA instantiation was already available to the consortium, for previous collaboration between KIT and ICCS. However, for the scopes of the TEAChER project, this description should be appropriately modified in order to be used also for academic purposes. In case we are studying the 2-D flow, then the VHDL description of Virtual FPGA (V-FPGA) is mapped onto an existing reconfigurable platform (e.g. provided by Altera or Xilinx), whereas the application mapping onto the VFPGA is performed with the extended version of 2-D MEANDER flow. Otherwise (3-D branch), the VHDL description of V-FPGA has to be appropriately modified in order to take into consideration inherent constraints posed by the third dimension (i.e. the existence of vertical connections that minimize the wirelength of long connections). Then, the V-FPGA is mapped onto an appropriate hardware platform (e.g. Virtex-7), which is aware about the 3-D integration, and application is implemented on top of V-FPGA (similar to the 2-D flavor of our methodology). Next, we describe in more detail the concept of V-FPGA.
The TEAChER Framework


Enhance the co-operation

Even though the participant universities (KIT and ICCS) have already cooperated successfully for different projects at the last years, the objectives addressed by the TEAChER project generates a new synergy about developing educational material at a field, where both of the partners have proven expertise. However, since this expertise is in complementary domains of the procedure of designing embedded systems, it is guaranteeing the successful outcome. Specifically, the partner from Germany (KIT) is working mostly on the hardware part of reconfigurable architectures, whereas the group from Greek university (ICCS), it has expertise on CAD algorithms and tools for performing architecture-level exploration, as well as application mapping onto reconfigurable platforms. Additionally, both groups have proven experience in using state-of-the-art platforms and tools provided by industrial sector for realizing demanding algorithms onto FPGAs.

Transfer knowledge based on the market's needs

Since the participant laboratories from the German and Greek universities have already established a tight co-operation (through research activities and projects) with research institutes and R&D departments of companies in the domain of reconfigurable architectures across the whole Europe, it is expected that the students that attend these lessons will earn industry-oriented skills, which potentially would be crucial for new jobs. Moreover, by strengthen the state-of-the-art knowledge in the domain of reconfigurable architectures and the supporting CAD tools, we expect to improve the competitiveness of young researchers not only inside the German and Greek countries, but worldwide.

Disseminate the knowledge and tools

By disseminate the educational material (e.g. books, software tools, etc) to the research community it is possible to achieve the maximum possible visibility for the outcomes of this project. Such a selection was already applied by the two partners regarding the former version of toolflows developed during the AMDREL project, which are public available to the internet for online execution.


The consortium of the TEAChER project comprises partners with an impressive academic track record and proven expertise on a variety of fields related to reconfigurable architectures and CAD tools. Through joining of the above partners' fields of expertise, the TEAChER project will focus on the development of an educational material for teaching advanced topics in the design of reconfigurable architectures, as well as the software tools that automate the procedures of architecture-level exploration of these platforms and perform application mapping onto them, with the usage of state-of-the-art technologies.

Institute for Information Processing Technologies (ITIV)

Contact Person:
Prof. Jurgen Becker

Karlsruhe Institute of Technology (KIT)
Engesserstr. 5, Bldg. 30.10, 76131 Karlsruhe, Germany
Phone: +49 721 608-42502
Fax: +49 721 608-42511

Institute of Communication and Computer Systems (ICCS)

Contact Person:
Prof. Dimitrios Soudris

National Technical University of Athens (NTUA)
School of Electrical & Computer Engineering
Microprocessors and Digital Systems Lab (MicroLab)
Iroon Polytechneiou 9, 15773, Zografou, Athens, Greece
Phone: +30 210 7724270
Fax: +30 210 7722428


During the TEAChER project, a number of lectures and laboratory excercises will be developed. Additionally, all the necessary infrastructure and software tools that enable remove access to those tools will also be developed in order to support the concept of virtual laboratories.

Xilinx Virtex-7
Xilinx Xynq
Xilinx Kintex-7

High-Level Synthesis (HLS)
Physical Implementation
Application Mapping
Bitstream Configuration

Virtual FPGA
2-D and 3-D Reconfigurable Architectures
Academic Toolflows

3 years project


  • K. Siozios and D. Soudris, "A Customizable Framework for Application Implementation onto 3-D FPGAs," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 11, pp. 1783-1796, Nov. 2016.
  • E. Sotiriou-Xanthopoulos, S. Xydis, Κ. Siozios, G. Economakos, and D. Soudris, "A Framework for Interconnection-Aware Domain-Specific Many-Accelerator Synthesis", ACM Trans. Embed. Comput. Syst. Vol. 16, No. 1, Article 8 (October 2016), 26 pages.
  • E. Sotiriou-Xanthopoulos, S. Xydis, K. Siozios, G. Economakos, and D. Soudris, "An Integrated Exploration and Virtual Platform Framework for Many-Accelerator Heterogeneous Systems", ACM Trans. Embed. Comput. Syst. 15, 3, Article 43 (March 2016), 26 pages.
  • P. Danassis, K. Siozios and D. Soudris, "ANT3D: Simultaneous Partitioning and Placement for 3-D FPGAs based on Ant Colony Optimization," in IEEE Embedded Systems Letters, vol. 8, no. 2, pp. 41-44, June 2016.
  • E. Sotiriou-Xanthopoulos, S. Xydis, K. Siozios, G. Economakos and D. Soudris, "Rapid prototyping and Design Space Exploration methodologies for many-accelerator systems", International Conference in Field-Programmable Logic and Applications (FPL), pp. 1–2, Sept. 2015, London, England.
  • E. Sotiriou-Xanthopoulos, L. Masing, K. Siozios, G. Economakos, D. Soudris and J. Becker, "An OpenCL-based framework for rapid virtual prototyping of heterogeneous architectures," International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Agios Konstantinos, Samos Island, Greece, 2016, pp. 372-377.
  • K. Siozios, I. Savidis and D. Soudris, "A framework for exploring alternative fault-tolerant schemes targeting 3-D reconfigurable architectures," International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Agios Konstantinos, Samos Island, Greece, 2016, pp. 336-341.
  • E. Sotiriou-Xanthopoulos, S. Xydis, K. Siozios and G. Economakos, "A virtual platform for exploring hierarchical interconnection for many-accelerator systems", Workshop on Virtual Prototyping of Parallel and Embedded Systems (VIPES), pp. 384–389, July 2015, Samos, Greece.
  • P. Danassis, K. Siozios and D. Soudris, "Parallel application placement onto 3-D reconfigurable architectures," 5th International Conference on Modern Circuits and Systems Technologies (MOCAST), Thessaloniki, 2016, pp. 1-4.
  • E. Sotiriou-Xanthopoulos, G.S. Percy Delicia, P. Figuli, K. Siozios, G. Economakos and J. Becker, "A power estimation technique for cycle-accurate higher-abstraction SystemC-based CPU models," in Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015 International Conference on, pp.70-77, 19-23 July 2015, doi: 10.1109/SAMOS.2015.7363661.
  • P. Figuli, C. Tradowsky, J.A. Lucio Martinez, H. Sidiropoulos, K. Siozios, H. Stenschke, D. Soudris, and J. Becker, "A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware"", International Symposium on Applied Reconfigurable Computing, pp. 311-320, Germany, 2015.
  • D. Diamantopoulos, S. Xydis, K. Siozios and D. Soudris, "Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures", Applied Reconfigurable Computing Workshop, pp. 117-128, 2015.
  • K. Siozios, P. Figuli, H. Sidiropoulos, C. Tradowsky, K. Maragos, S. P. Delicia, D. Soudris and J. Becker, “TEAChER: TEach AdvanCEd Reconfigurable architectures and tools”, 11th Int. Workshop on Applied Reconfigurable Computing (ARC), pp. 103-114, April 2015.
  • V. Tsoutsouras, D. Azariadi, S. Xydis and D. Soudris, “Effective Learning and Filtering of Faulty Heart-Beats for Advanced ECG Arrhythmia Detection using MIT-BIH Database”, 5th EAI International Conference on Wireless Mobile Communication and Healthcare (Mobihealth), 2015.


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